Low-power design-for-test implementation on phase-locked loop design
نویسندگان
چکیده
منابع مشابه
Design and Implementation of Low Ripple Low Power Digital Phase-Locked Loop
We propose a phase-locked loop (PLL) architecture which reduces double frequency ripple without increasing the order of loop filter. Proposed architecture uses quadrature numerically–controlled oscillator (NCO) to provide two output signals with phase difference of π / 2 . One of them is subtracted from the input signal before multiplying with the other output of NCO. The system also provides s...
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The fundamental design concepts for phase-locked loops implemented with integrated circuits are outlined. The necessary equations required to evaluate the basic loop performance are given in conjunction with a brief design example. NOTE This document contains references to obsolete part numbers and is offered for technical information only.
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ژورنال
عنوان ژورنال: Measurement and Control
سال: 2019
ISSN: 0020-2940
DOI: 10.1177/0020294019858089